Sciweavers

7 search results - page 1 / 2
» Running a Quantum Circuit at the Speed of Data
Sort
View
ISCA
2008
IEEE
113views Hardware» more  ISCA 2008»
14 years 5 months ago
Running a Quantum Circuit at the Speed of Data
We analyze circuits for a number of kernels from popular quantum computing applications, characterizing the hardware resources necessary to take ancilla preparation off the critic...
Nemanja Isailovic, Mark Whitney, Yatish Patel, Joh...
TCAD
2002
115views more  TCAD 2002»
13 years 10 months ago
Analytical models for crosstalk excitation and propagation in VLSI circuits
We develop a general methodology to analyze crosstalk effects that are likely to cause errors in deep submicron high speed circuits. We focus on crosstalk due to capacitive coupli...
Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
FPGA
2004
ACM
234views FPGA» more  FPGA 2004»
14 years 2 months ago
An embedded true random number generator for FPGAs
Field Programmable Gate Arrays (FPGAs) are an increasingly popular choice of platform for the implementation of cryptographic systems. Until recently, designers using FPGAs had le...
Paul Kohlbrenner, Kris Gaj
ISVLSI
2008
IEEE
136views VLSI» more  ISVLSI 2008»
14 years 5 months ago
A Real Case of Significant Scan Test Cost Reduction
With the advent of nanometer technologies, the design size of integrated circuits is getting larger and the operation speed is getting faster. As a consequence, test cost is becom...
Selina Sha, Bruce Swanson
HIPEAC
2011
Springer
12 years 10 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem