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EUROPAR
2009
Springer
14 years 20 days ago
A Buffer Space Optimal Solution for Re-establishing the Packet Order in a MPSoC Network Processor
We consider a multi-processor system-on-chip destined for streaming applications. An application is composed of one input and one output queue and in-between, several levels of ide...
Daniela Genius, Alix Munier Kordon, Khouloud Zine ...
TCAD
2008
127views more  TCAD 2008»
13 years 8 months ago
Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration
Abstract--Multimedia and DSP applications have several computationally intensive kernels which are often offloaded and accelerated by application-specific hardware. This paper pres...
Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozor...
CCGRID
2006
IEEE
14 years 2 months ago
Integrating the HLA RTI Services with Scilab
This paper describes the integration of the High Level Architecture (HLA), an IEEE standard for distributed interactive simulation, with a scientific software package (Scilab) and...
Thitima Theppaya, Pichaya Tandayya, Chatchai Janta...
DAC
2004
ACM
14 years 9 months ago
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
Ashish Srivastava, Dennis Sylvester, David Blaauw
IPPS
2009
IEEE
14 years 3 months ago
Application profiling on Cell-based clusters
In this paper, we present a methodology for profiling parallel applications executing on the IBM PowerXCell 8i (commonly referred to as the “Cell” processor). Specifically, we...
Hikmet Dursun, Kevin J. Barker, Darren J. Kerbyson...