36 search results - page 1 / 8 » Runtime and quality tradeoffs in FPGA placement and routing |
FPGA
2001
ACM
14 years 2 months ago
2001
ACM
FPL
1997
Springer
14 years 1 months ago
1997
Springer
We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published FPG...
ICCAD
2003
IEEE
14 years 6 months ago
2003
IEEE
High quality placement results are always produced at the cost of significant runtimes. In this paper, we study the trade-off between the overall quality and the runtime for stand...
FPL
2007
Springer
14 years 3 months ago
2007
Springer
Reconfigurable computing entails the utilization of a generalpurpose processor augmented with a reconfigurable hardware structure (usually an FPGA). Normally, a complete recon...
FPGA
2010
ACM
14 years 6 months ago
2010
ACM
Placement based on simulated annealing is in dominant use in the FPGA community due to its superior quality of result (QoR). However, given the progression of FPGA device capacity...