24 search results - page 3 / 5 » SAARA: a simulated annealing algorithm for test pattern gene... |
EVOW
2001
Springer
13 years 12 months ago
2001
Springer
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
FPL
2004
Springer
14 years 26 days ago
2004
Springer
Abstract. We present an evaluation of accelerating fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is fre...
ICES
2000
Springer
13 years 11 months ago
2000
Springer
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
ATS
2000
IEEE
13 years 12 months ago
2000
IEEE
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
VLSID
2005
IEEE
14 years 1 months ago
2005
IEEE
During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying “useless” test vectors that do not contribute t...