Sciweavers

61 search results - page 1 / 13
» SAMBA-Bus: A High Performance Bus Architecture for System-on...
Sort
View
DAC
2001
ACM
14 years 9 months ago
Latency-Driven Design of Multi-Purpose Systems-On-Chip
Milenko Drinic UCLA Computer Science Dep. 4732 Boelter Hall Los Angeles, CA 90095-1596 milenko@cs.ucla.edu Darko Kirovski Microsoft Research One Microsoft Way Redmond, WA 98052 da...
Seapahn Meguerdichian, Milenko Drinic, Darko Kirov...
BWCCA
2010
13 years 2 months ago
Advanced Design Issues for OASIS Network-on-Chip Architecture
Network-on-Chip (NoC) architectures provide a good way of realizing efficient interconnections and largely alleviate the limitations of bus-based solutions. NoC has emerged as a so...
Kenichi Mori, Adam Esch, Abderazek Ben Abdallah, K...
ICCAD
2003
IEEE
129views Hardware» more  ICCAD 2003»
14 years 4 months ago
SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips
A high performance communication architecture, SAMBA-bus, is proposed in this paper. In SAMBA-bus, multiple compatible bus transactions can be performed simultaneously with only a...
Ruibing Lu, Cheng-Kok Koh
ASPDAC
2004
ACM
88views Hardware» more  ASPDAC 2004»
14 years 1 months ago
A high performance bus communication architecture through bus splitting
Abstract— A split shared-bus architecture with multiple simultaneous bus accesses is proposed. Compared to traditional bus architectures, the performance of proposed architecture...
Ruibing Lu, Cheng-Kok Koh
DAC
2000
ACM
14 years 9 months ago
COSY communication IP's
The Esprit/OMI-COSY project defines transaction-levels to set-up the exchange of IP's in separating function from architecture and body-behavior from proprietary interfaces. ...
Erwin A. de Kock, Frédéric Pé...