Sciweavers

61 search results - page 8 / 13
» SAMBA-Bus: A High Performance Bus Architecture for System-on...
Sort
View
ASPDAC
2005
ACM
142views Hardware» more  ASPDAC 2005»
13 years 10 months ago
An AMBA AHB-based reconfigurable SOC architecture using multiplicity of dedicated flyby DMA blocks
– We propose a System-on-Chip (SoC) architecture for reconfigurable applications based on the AMBA HighSpeed Bus (AHB). The architecture features multiple low-area flyby DMA bloc...
Adeoye Olugbon, Sami Khawam, Tughrul Arslan, Ioann...
CODES
2003
IEEE
14 years 1 months ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
DAC
2006
ACM
14 years 9 months ago
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sh...
CSREAESA
2006
13 years 9 months ago
A Dual-core Embedded System-on-Chip Architecture for Multimedia Signal Processing Applications
- This paper presents a dual-core embedded System-on-Chip for a wide range of application fields with particularly high processing demands, including general signal processing, vid...
Hong Yue, Kui Dai, Zhiying Wang
AINA
2009
IEEE
13 years 5 months ago
Evaluating the Performance of Network Protocol Processing on Multi-core Systems
Improvements at the physical network layer have enabled technologies such as 10 Gigabit Ethernet. Single core end-systems are unable to fully utilise these networks, due to limite...
Matthew Faulkner, Andrew Brampton, Stephen Pink