71 search results - page 1 / 15 » SEP: Simulation framework to evaluate digital hardware archi... |
ESM
2000
13 years 9 months ago
2000
Know-how is the most useful mean for designing new processors before a complete hardware description. The integration rate is increasing very quickly and the timeto-market has to ...
SBACPAD
2007
IEEE
14 years 1 months ago
2007
IEEE
ESM
1998
13 years 9 months ago
1998
In order to reduce the cost, the time-to-market and to make the most pertinent choices, it becomes essential to allow designers to evaluate, very soon in the design phase, a given...
ICCD
1993
IEEE
13 years 11 months ago
1993
IEEE
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
: The theoretical study of quantum computation has yielded efficient algorithms for some traditionally hard problems. Correspondingly, experimental work on the underlying physical...