71 search results - page 5 / 15 » SEP: Simulation framework to evaluate digital hardware archi... |
FPGA
2003
ACM
14 years 2 months ago
2003
ACM
This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contri...
ISCAS
2005
IEEE
14 years 2 months ago
2005
IEEE
—Systems on chip are more and more heterogeneous and include software, analog/RF and digital hardware, and non-electronic components such as sensors or actuators. The design and ...
SBACPAD
2004
IEEE
13 years 10 months ago
2004
IEEE
High-performance superscalar processors are designed with the help of complex simulation environment. The simulation infrastructure permits to validate the processor instruction s...
DSD
2002
IEEE
14 years 1 months ago
2002
IEEE
This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
Instruction set simulators are common tools used for the development of new architectures and embedded software among countless other functions. This paper presents a framework th...