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ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
13 years 11 months ago
A case for FAME: FPGA architecture model execution
Given the multicore microprocessor revolution, we argue that the architecture research community needs a dramatic increase in simulation capacity. We believe FPGA Architecture Mod...
Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bi...
NOSSDAV
2010
Springer
13 years 11 months ago
RTP-miner: a real-time security framework for RTP fuzzing attacks
Real-time Transport Protocol (RTP) is a widely adopted standard for transmission of multimedia traffic in Internet telephony (commonly known as VoIP). Therefore, it is a hot poten...
M. Ali Akbar, Muddassar Farooq
ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
13 years 11 months ago
Piranha: a scalable architecture based on single-chip multiprocessing
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
Luiz André Barroso, Kourosh Gharachorloo, R...
SIGGRAPH
1999
ACM
13 years 11 months ago
Six Degree-of-Freedom Haptic Rendering Using Voxel Sampling
A simple, fast, and approximate voxel-based approach to 6DOF haptic rendering is presented. It can reliably sustain a 1000 Hz haptic refresh rate without resorting to asynchronous...
William A. McNeely, Kevin D. Puterbaugh, James J. ...
SC
2004
ACM
14 years 3 days ago
A Performance and Scalability Analysis of the BlueGene/L Architecture
This paper is structured as follows. Section 2 gives an architectural description of BlueGene/L. Section 3 analyzes the issue of “computational noise” – the effect that the o...
Kei Davis, Adolfy Hoisie, Greg Johnson, Darren J. ...