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IJPP
2000
94views more  IJPP 2000»
13 years 7 months ago
Path Analysis and Renaming for Predicated Instruction Scheduling
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
Lori Carter, Beth Simon, Brad Calder, Larry Carter...
ICCAD
1994
IEEE
95views Hardware» more  ICCAD 1994»
13 years 11 months ago
Provably correct high-level timing analysis without path sensitization
- This paper addresses the problem of true delay estimation during high level design. The existing delay estimation techniques either estimate the topological delay of the circuit ...
Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
ICCD
2004
IEEE
113views Hardware» more  ICCD 2004»
14 years 4 months ago
End-to-End Testability Analysis and DfT Insertion for Mixed-Signal Paths
Increasing system complexity and test cost demands new system-level solutions for mixed-signal systems. In this paper, we present a testability analysis and DfT insertion methodol...
Sule Ozev, Alex Orailoglu
DATE
2006
IEEE
105views Hardware» more  DATE 2006»
14 years 1 months ago
Statistical timing analysis with path reconvergence and spatial correlations
State of the art statistical timing analysis (STA) tools often yield less accurate results when timing variables become correlated. Spatial correlation and correlation caused by p...
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
CC
2006
Springer
125views System Software» more  CC 2006»
13 years 11 months ago
Path-Based Reuse Distance Analysis
Abstract. Profiling can effectively analyze program behavior and provide critical information for feedback-directed or dynamic optimizations. Based on memory profiling, reuse dista...
Changpeng Fang, Steve Carr, Soner Önder, Zhen...