202 search results - page 15 / 41 » SOC Test Scheduling Using Simulated Annealing |
VLSID
1998
IEEE
13 years 11 months ago
1998
IEEE
With several commercial tools becoming available, the high-level synthesis of applicationspeci c integrated circuits is nding wide spread acceptance in VLSI industry today. Existi...
DSD
2010
IEEE
13 years 7 months ago
2010
IEEE
—Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated i...
ICCD
1997
IEEE
13 years 11 months ago
1997
IEEE
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
KBSE
2003
IEEE
14 years 22 days ago
2003
IEEE
The use of techniques for automating the generation of software test cases is very important as it can reduce the time and cost of this process. The latest methods for automatic g...
CORR
2007
Springer
13 years 7 months ago
2007
Springer
Real Options for Project Schedules (ROPS) has three recursive sampling/optimization shells. An outer Adaptive Simulated Annealing (ASA) optimization shell optimizes parameters of ...