202 search results - page 5 / 41 » SOC Test Scheduling Using Simulated Annealing |
CEC
2003
IEEE
14 years 22 days ago
2003
IEEE
Abstract- Simulated annealing (SA) is an effective general heuristic method for solving many combinatorial optimization problems. This paper deals with two problems in SA. One is ...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
This paper presents a wrapper and TAM co-optimization method for reuse of SoC functional interconnects to minimize test time under area constraint. The proposed method consists of...
ATS
2005
IEEE
14 years 1 months ago
2005
IEEE
11 Due to the increasing test data volume needed to test corebased System-on-Chip, several test scheduling techniques minimizing the test application time have been proposed. In co...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
DFT
2006
IEEE
14 years 1 months ago
2006
IEEE
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...