175 search results - page 17 / 35 » SOC Testing Methodology and Practice |
VLSID
2002
IEEE
14 years 10 months ago
2002
IEEE
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
CHI
2010
ACM
14 years 4 months ago
2010
ACM
Although usability methods are widely used for evaluating conventional graphical user interfaces and websites, there is a growing concern that current approaches are inadequate fo...
IEEEPACT
2006
IEEE
14 years 3 months ago
2006
IEEE
Transactional memory is an attractive design concept for scalable multiprocessors because it offers efficient lock-free synchronization and greatly simplifies parallel software....
DAC
2008
ACM
14 years 10 months ago
2008
ACM
C++ based verification methodologies are now emerging as the preferred method for SOC design. However most of the verification involving the C++ models are simulation based. The c...
FPGA
2007
ACM
14 years 1 months ago
2007
ACM
Progress in reconfigurable hardware technology allows the implementation of complete SoCs in today's FPGAs. In the context design for reliability, software checkpointing is a...