Sciweavers

17 search results - page 3 / 4
» SPARC16: A New Compression Approach for the SPARC Architectu...
Sort
View
DATE
2009
IEEE
76views Hardware» more  DATE 2009»
14 years 2 months ago
LFSR-based test-data compression with self-stoppable seeds
—The main disadvantage of LFSR-based compression is that it should be usually combined with a constrained ATPG process, and, as a result, it cannot be effectively applied to IP c...
M. Koutsoupia, Emmanouil Kalligeros, Xrysovalantis...
FCCM
2004
IEEE
130views VLSI» more  FCCM 2004»
13 years 11 months ago
Hyperreconfigurable Architectures for Fast Run Time Reconfiguration
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit changing needs of a computation during run time. The increasing...
Sebastian Lange, Martin Middendorf
ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
14 years 1 months ago
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
Nathan Clark, Jason A. Blome, Michael L. Chu, Scot...
JCIT
2008
165views more  JCIT 2008»
13 years 7 months ago
Adaptive Source pixel based Prediction for Lossless Intra Coding of H.264 MPEG-4 /AVC
A new prediction for lossless intra coding technique employs source pixel based prediction in contrast to source block based prediction is presented as an enhancement of H.264/MPE...
N. Krishnan, P. Vijayalakshmi, R. K. Selvakumar, S...
MM
2000
ACM
166views Multimedia» more  MM 2000»
14 years 3 days ago
A video-based rendering acceleration algorithm for interactive walkthroughs
We present a new approach for faster rendering of large synthetic environments using video-based representations. We decompose the large environment into cells and pre-compute vid...
Andrew Wilson, Ming C. Lin, Boon-Lock Yeo, Minerva...