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PATMOS
2004
Springer
14 years 1 months ago
Sleepy Stack Reduction of Leakage Power
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as...
Jun-Cheol Park, Vincent John Mooney III, Philipp P...
FPGA
2005
ACM
122views FPGA» more  FPGA 2005»
14 years 1 months ago
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be powe...
Yan Lin, Fei Li, Lei He
DATE
2010
IEEE
158views Hardware» more  DATE 2010»
14 years 24 days ago
Energy- and endurance-aware design of phase change memory caches
—Phase change memory (PCM) is one of the most promising technology among emerging non-volatile random access memory technologies. Implementing a cache memory using PCM provides m...
Yongsoo Joo, Dimin Niu, Xiangyu Dong, Guangyu Sun,...
INFOCOM
1999
IEEE
14 years 3 hour ago
A Fast IP Routing Lookup Scheme for Gigabit Switching Routers
One of the key design issues for the new generation IP routers is the route lookup mechanism. For each incoming IP packet, the IP routing requires to perform a longest prefix match...
Nen-Fu Huang, Shi-Ming Zhao, Jen-Yi Pan, Chi-An Su
ICCD
2004
IEEE
106views Hardware» more  ICCD 2004»
14 years 4 months ago
Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction
Leakage current is a key factor in IC power consumption even in the active operating mode. We investigate the simultaneous optimization of gate size and threshold voltage to reduc...
Feng Gao, John P. Hayes