2020 search results - page 24 / 404 » Scalable Instruction-Level Parallelism. |
HPCA
2003
IEEE
14 years 9 months ago
2003
IEEE
To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundament...
HPCA
2001
IEEE
14 years 9 months ago
2001
IEEE
Value prediction is a relatively new technique to increase the Instruction Level Parallelism (ILP) in future microprocessors. An important problem when designing a value predictor...
IEEEPACT
2007
IEEE
14 years 3 months ago
2007
IEEE
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
SAMOS
2004
Springer
14 years 2 months ago
2004
Springer
— Architectural resources and program recurrences are the main limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops, the most time-consuming pa...
ISLPED
2003
ACM
14 years 2 months ago
2003
ACM
This paper develops a technique that uniquely combines the advantages of static scheduling and dynamic scheduling to reduce the energy consumed in modern superscalar processors wi...