2020 search results - page 32 / 404 » Scalable Instruction-Level Parallelism. |
CC
2003
Springer
14 years 2 months ago
2003
Springer
Abstract. The register allocation in loops is generally performed after or during the software pipelining process. This is because doing a conventional register allocation at firs...
ISCA
2002
IEEE
14 years 1 months ago
2002
IEEE
The impact of pipeline length on the performance of a microprocessor is explored both theoretically and by simulation. An analytical theory is presented that shows two opposing ar...
MICRO
2000
IEEE
14 years 1 months ago
2000
IEEE
Value prediction breaks data dependencies in a program thereby creating instruction level parallelism that can increase program performance. Hardware based value prediction techni...
MICRO
1999
IEEE
14 years 1 months ago
1999
IEEE
Since there is generally insufficient instruction level parallelism within a single basic block, higher performance is achieved by speculatively scheduling operations in superbloc...
ISCA
1998
IEEE
14 years 1 months ago
1998
IEEE
Modern processors improve instruction level parallelism by speculation. The outcome of data and control decisions is predicted, and the operations are speculatively executed and o...