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IEEEPACT
2008
IEEE
14 years 4 months ago
2008
IEEE
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
ISVLSI
2008
IEEE
14 years 4 months ago
2008
IEEE
Powerful branch predictors along with a large branch target buffer (BTB) are employed in superscalar processors for instruction-level parallelism exploitation. However, the large ...
MICRO
2008
IEEE
14 years 4 months ago
2008
IEEE
— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed arch...
DSN
2007
IEEE
14 years 4 months ago
2007
IEEE
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
ISORC
2007
IEEE
14 years 4 months ago
2007
IEEE
As E-businesses are becoming ubiquitous, enhancing the performance and scalability of ebusiness systems has become an increasingly important topic of investigation. As Vitruvius (...