2020 search results - page 5 / 404 » Scalable Instruction-Level Parallelism. |
MICRO
2000
IEEE
13 years 8 months ago
2000
IEEE
High-performance microprocessors are currently designed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their de...
IEEEPACT
1999
IEEE
14 years 1 months ago
1999
IEEE
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
IPPS
2000
IEEE
14 years 1 months ago
2000
IEEE
The newly introduced Microprocessor Architecture for Java Computing MAJC supports parallelism in a hierarchy of levels: multiprocessors on chip,vertical micro threading, instruct...
EUROMICRO
1997
IEEE
14 years 1 months ago
1997
IEEE
CMOS technology should, over the next few years, reach lithography of under 0.1¡ . This provides a die area improvement of a factor of 10 over today’s technology. What is the b...
IJPP
2000
13 years 8 months ago
2000
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...