40 search results - page 2 / 8 » Scalable cache memory design for large-scale SMT architectur... |
MICRO
2010
IEEE
13 years 7 months ago
2010
IEEE
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
ICDCS
1999
IEEE
14 years 28 days ago
1999
IEEE
In this paper, we describe the design and implementation of an integrated architecture for cache systems that scale to hundreds or thousands of caches with thousands to millions o...
DATE
1997
IEEE
14 years 25 days ago
1997
IEEE
In this paper a parametrizable architecture of a motion estimator (ME) is presented. The ME is designed as a generic full pixel calculation module which can be adopted for di eren...
SC
1992
ACM
14 years 21 days ago
1992
ACM
We are currently developing Willow, a shared-memory multiprocessor whose design provides system capacity and performance capable of supporting over a thousand commercial microproc...
MICRO
2006
IEEE
14 years 2 months ago
2006
IEEE
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...