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HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and hi...
VLSID
2003
IEEE
2003
IEEE
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
14 years 8 months ago
We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input blocks efficiently. In the IDCT mode, the latency of the processo...
HPCA
2006
IEEE
14 years 8 months ago
2006
IEEE
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
EDBT
2004
ACM
14 years 7 months ago
2004
ACM
GRID technology, emerging in the late nineties, has evolved from a metacomputing architecture towards a pervasive computation and information utility. However, the architectural de...
DSN
2007
IEEE
14 years 2 months ago
2007
IEEE
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...