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JSA
2000
116views more  JSA 2000»
15 years 4 months ago
Distributed vector architectures
Integrating processors and main memory is a promising approach to increase system performance. Such integration provides very high memory bandwidth that can be exploited efficientl...
Stefanos Kaxiras
IADIS
2009
15 years 2 months ago
A strategy for cost efficient distributed data storage for in-memory OLAP
With the availability of inexpensive blade servers featuring 32 GB or more of main memory, memory-based engines such as the SAP NetWeaver Business Warehouse Accelerator are coming...
Olga Mordvinova, Oleksandr Shepil, Thomas Ludwig 0...
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 9 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
EUROSYS
2007
ACM
16 years 1 months ago
Sprint: a middleware for high-performance transaction processing
Sprint is a middleware infrastructure for high performance and high availability data management. It extends the functionality of a standalone in-memory database (IMDB) server to ...
Lásaro J. Camargos, Fernando Pedone, Marcin...
ICASSP
2011
IEEE
14 years 8 months ago
A dynamic approach to the selection of high order n-grams in phonotactic language recognition
Due to computational bounds, most SVM-based phonotactic language recognition systems consider only low-order n-grams (up to n = 3), thus limiting the potential performance of this...
Mikel Peñagarikano, Amparo Varona, Luis Jav...