Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs

On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-performance processors, high-end embedded cores are moving from singlelevel on chip caches to a two-level on-chip cache hierarchy. Whereas in the embedded world there is general consensus on L1 private caches, for L2 there is still not a dominant architectural paradigm. Cache architectures that work for high performance computers turn out to be inefficient for embedded systems (mainly due to power-efficiency issues). This paper presents a virtual platform for design space exploration of L2 cache architectures in low-power Multi-Processor-Systemson-Chip (MPSoCs). The tool contains several L2 caches templates, and new architectures can be easily added using our flexible plug-in system. Given a set of constrains for a specific system (power, area, performance), our tool will perform extensive exploration to find the...

• Type: Conference
• Year: 2010
• Where: GLVLSI
• Authors: Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia Del Valle
• Keywords: Cache Architectures, GLVLSI 2010, L2 Cache, Two-level On-chip Cache, VLSI