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HPCA
2006
IEEE
14 years 10 months ago
Efficient instruction schedulers for SMT processors
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
Joseph J. Sharkey, Dmitry V. Ponomarev
HPCA
2006
IEEE
14 years 10 months ago
Software-hardware cooperative memory disambiguation
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...
Ruke Huang, Alok Garg, Michael C. Huang
MICRO
2006
IEEE
89views Hardware» more  MICRO 2006»
14 years 3 months ago
DMDC: Delayed Memory Dependence Checking through Age-Based Filtering
One of the main challenges of modern processor design is the implementation of a scalable and efficient mechanism to detect memory access order violations as a result of out-of-o...
Fernando Castro, Luis Piñuel, Daniel Chaver...
ICCS
2004
Springer
14 years 3 months ago
A Real-Time Total Order Multicast Protocol
Abstract. We describe, analyze and submit results of a real-time total order multicast protocol developed on a distributed real-time system architecture that consists of hierarchic...
Kayhan Erciyes, Ahmet Sahan
GECCO
2004
Springer
175views Optimization» more  GECCO 2004»
14 years 3 months ago
An Architecture for Massive Parallelization of the Compact Genetic Algorithm
This paper presents an architecture which is suitable for a massive parallelization of the compact genetic algorithm. The approach is scalable, has low synchronization costs, and i...
Fernando G. Lobo, Cláudio F. Lima, Hugo Mar...