433 search results - page 16 / 87 » Scale in Chip Interconnect requires Network Technology |
ISCA
2010
IEEE
14 years 2 months ago
2010
IEEE
Continued device scaling enables microprocessors and other systems-on-chip (SoCs) to increase their performance, functionality, and hence, complexity. Simultaneously, relentless s...
DSN
2006
IEEE
14 years 3 months ago
2006
IEEE
The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects. In particular, single event upsets, such as soft errors, and hard faults are ...
ISLPED
2005
ACM
14 years 3 months ago
2005
ACM
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
ISPD
1998
ACM
14 years 2 months ago
1998
ACM
This paper describes an important new facility for timing-driven design applications within the new CHDStd standard for a SEMATECH design system for large complex chips. We first ...
RECONFIG
2009
IEEE
14 years 4 months ago
2009
IEEE
—We envision that future FPGA will use a hardwired network on chip (HWNoC) [14] as a unified interconnect for functional communications (data and control) as well as configurat...