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» Scale in Chip Interconnect requires Network Technology
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ACSC
2006
IEEE
14 years 1 months ago
Modelling layer 2 and layer 3 device bandwidths using B-node theory
Modern computer networks contain an amalgamation of devices and technologies, with the performance exhibited by each central to digital communications. Varieties of methods exist ...
S. Cikara, Stanislaw P. Maj, David T. Shaw
BMCBI
2007
146views more  BMCBI 2007»
13 years 7 months ago
Bayesian hierarchical model for transcriptional module discovery by jointly modeling gene expression and ChIP-chip data
Background: Transcriptional modules (TM) consist of groups of co-regulated genes and transcription factors (TF) regulating their expression. Two high-throughput (HT) experimental ...
Xiangdong Liu, Walter J. Jessen, Siva Sivaganesan,...
ICS
2005
Tsinghua U.
14 years 28 days ago
High performance support of parallel virtual file system (PVFS2) over Quadrics
Parallel I/O needs to keep pace with the demand of high performance computing applications on systems with ever-increasing speed. Exploiting high-end interconnect technologies to ...
Weikuan Yu, Shuang Liang, Dhabaleswar K. Panda
ISCA
2007
IEEE
196views Hardware» more  ISCA 2007»
14 years 1 months ago
Anton, a special-purpose machine for molecular dynamics simulation
The ability to perform long, accurate molecular dynamics (MD) simulations involving proteins and other biological macromolecules could in principle provide answers to some of the ...
David E. Shaw, Martin M. Deneroff, Ron O. Dror, Je...
ATAL
2008
Springer
13 years 9 months ago
Decentralised coordination of low-power embedded devices using the max-sum algorithm
This paper considers the problem of performing decentralised coordination of low-power embedded devices (as is required within many environmental sensing and surveillance applicat...
Alessandro Farinelli, Alex Rogers, Adrian Petcu, N...