860 search results - page 149 / 172 » Scaling Up Software Architecture Evaluation Processes |
BMCBI
2007
13 years 7 months ago
2007
Background: It is becoming increasingly important for researchers to be able to scan through large genomic regions for transcription factor binding sites or clusters of binding si...
MICRO
2008
IEEE
14 years 2 months ago
2008
IEEE
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...
EXPERT
1998
13 years 7 months ago
1998
This article illustrates the complexities of real-world planning and how we can create AI planning systems to address them. We describe the IMACS Project (Interactive Manufacturab...
PPOPP
2009
ACM
14 years 8 months ago
2009
ACM
The efficient mapping of program parallelism to multi-core processors is highly dependent on the underlying architecture. This paper proposes a portable and automatic compiler-bas...
MICRO
1995
IEEE
13 years 11 months ago
1995
IEEE
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...