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ISQED
2002
IEEE
83views Hardware» more  ISQED 2002»
14 years 21 days ago
A Hybrid BIST Architecture and Its Optimization for SoC Testing
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus
DSN
2002
IEEE
14 years 22 days ago
A Portable and Fault-Tolerant Microprocessor Based on the SPARC V8 Architecture
The architecture and implementation of the LEON-FT processor is presented. LEON-FT is a fault-tolerant 32-bit processor based on the SPARC V8 instruction set. The processors toler...
Jiri Gaisler
IPPS
2007
IEEE
14 years 2 months ago
Base Operating System Provisioning and Bringup for a Commercial Supercomputer
Commercial Scale-Out is a new research project at IBM Research. Its main goal is to investigate and develop technologies for the use of large scale parallelism in commercial appli...
David Daly, Jong Hyuk Choi, José E. Moreira...
NSDI
2008
13 years 10 months ago
DieCast: Testing Distributed Systems with an Accurate Scale Model
Large-scale network services can consist of tens of thousands of machines running thousands of unique software configurations spread across hundreds of physical networks. Testing ...
Diwaker Gupta, Kashi Venkatesh Vishwanath, Amin Va...
CASES
2006
ACM
13 years 11 months ago
Probabilistic arithmetic and energy efficient embedded signal processing
Probabilistic arithmetic, where the ith output bit of addition and multiplication is correct with a probability pi, is shown to be a vehicle for realizing extremely energy-efficie...
Jason George, B. Marr, Bilge E. S. Akgul, Krishna ...