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» Scaling Up Software Architecture Evaluation Processes
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ISCA
2000
IEEE
90views Hardware» more  ISCA 2000»
14 years 8 days ago
A scalable approach to thread-level speculation
While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the re...
J. Gregory Steffan, Christopher B. Colohan, Antoni...
DAWAK
2008
Springer
13 years 9 months ago
Efficient Data Distribution for DWS
The DWS (Data Warehouse Striping) technique is a data partitioning approach especially designed for distributed data warehousing environments. In DWS the fact tables are distribute...
Raquel Almeida, Jorge Vieira, Marco Vieira, Henriq...
PACS
2004
Springer
112views Hardware» more  PACS 2004»
14 years 1 months ago
Low-Overhead Core Swapping for Thermal Management
Technology scaling trends and the limitations of packaging and cooling have intensified the need for thermally efficient architectures and architecture-level temperature managemen...
Eren Kursun, Glenn Reinman, Suleyman Sair, Anahita...
DAC
2004
ACM
14 years 8 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
14 years 1 months ago
An SPU reference model for simulation, random test generation and verification
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...
Yukio Watanabe, Balazs Sallay, Brad W. Michael, Da...