Sciweavers

454 search results - page 3 / 91
» Scaling an RNS Number Using the Core Function
Sort
View
ASPDAC
2007
ACM
101views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses
Abstract--An integrated test scheduling methodology for multiprocessor System-on-Chips (SOC) utilizing the functional buses for test data delivery is described. The proposed method...
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orail...
GVD
2009
191views Database» more  GVD 2009»
13 years 5 months ago
Query Processing on Multi-Core Architectures
The upcoming generation of computer hardware poses several new challenges for database developers and engineers. Software in general and database management systems (DBMSs) in par...
Frank Huber, Johann Christoph Freytag
ISQED
2003
IEEE
92views Hardware» more  ISQED 2003»
14 years 20 days ago
Parameterized Macrocells with Accurate Delay Models for Core-Based Designs
In this paper we propose a new design methodology targeted for core-based designs using parameterized macrocells (PMC’s). This methodology provides the flexibility for instance...
Makram M. Mansour, Mohammad M. Mansour, Amit Mehro...
PPL
2011
12 years 10 months ago
Mpi on millions of Cores
Petascale parallel computers with more than a million processing cores are expected to be available in a couple of years. Although MPI is the dominant programming interface today ...
Pavan Balaji, Darius Buntinas, David Goodell, Will...
GLVLSI
2009
IEEE
170views VLSI» more  GLVLSI 2009»
13 years 11 months ago
Physical unclonable function and true random number generator: a compact and scalable implementation
Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signat...
Abhranil Maiti, Raghunandan Nagesh, Anand Reddy, P...