1218 search results - page 196 / 244 » Scaling up a |
CVPR
2012
IEEE
12 years 15 days ago
2012
IEEE
In this paper, we propose a rank minimization method to fuse the predicted confidence scores of multiple models, each of which is obtained based on a certain kind of feature. Spe...
HPCA
2009
IEEE
14 years 10 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
HPCA
2005
IEEE
14 years 10 months ago
2005
IEEE
Simultaneous multithreading (SMT) and chip multiprocessing (CMP) both allow a chip to achieve greater throughput, but their relative energy-efficiency and thermal properties are s...
ASPLOS
2010
ACM
14 years 4 months ago
2010
ACM
Growing transistor counts, limited power budgets, and the breakdown of voltage scaling are currently conspiring to create a utilization wall that limits the fraction of a chip tha...
ISCA
2007
IEEE
14 years 4 months ago
2007
IEEE
With increasing speed and power density, high-performance memories, including FB-DIMM (Fully Buffered DIMM) and DDR2 DRAM, now begin to require dynamic thermal management (DTM) a...