1218 search results - page 196 / 244 » Scaling up a |
205
Voted
CVPR
2012
IEEE
13 years 8 months ago
2012
IEEE
In this paper, we propose a rank minimization method to fuse the predicted confidence scores of multiple models, each of which is obtained based on a certain kind of feature. Spe...
175
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HPCA
2009
IEEE
16 years 6 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
146
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HPCA
2005
IEEE
16 years 6 months ago
2005
IEEE
Simultaneous multithreading (SMT) and chip multiprocessing (CMP) both allow a chip to achieve greater throughput, but their relative energy-efficiency and thermal properties are s...
144
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ASPLOS
2010
ACM
16 years 27 days ago
2010
ACM
Growing transistor counts, limited power budgets, and the breakdown of voltage scaling are currently conspiring to create a utilization wall that limits the fraction of a chip tha...
164
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ISCA
2007
IEEE
16 years 11 days ago
2007
IEEE
With increasing speed and power density, high-performance memories, including FB-DIMM (Fully Buffered DIMM) and DDR2 DRAM, now begin to require dynamic thermal management (DTM) a...