1263 search results - page 107 / 253 » Scatter-Add in Data Parallel Architectures |
IEEEPACT
2009
IEEE
14 years 4 months ago
2009
IEEE
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
HPDC
1999
IEEE
14 years 1 months ago
1999
IEEE
Modern scientific computing involves organizing, moving, visualizing, and analyzing massive amounts of data at multiple sites around the world. The technologies, the middleware se...
HPCA
2003
IEEE
14 years 10 months ago
2003
IEEE
To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundament...
IEEEPACT
2002
IEEE
14 years 2 months ago
2002
IEEE
This paper presents a new modulo scheduling algorithm for clustered microarchitectures. The main feature of the proposed scheme is that the assignment of instructions to clusters ...
LSSC
2005
Springer
14 years 3 months ago
2005
Springer
A new parallel algorithm for signal processing and a parallel systolic architecture of a robust constant false alarm rate (CFAR) processor with post-detection integration and adap...