1263 search results - page 204 / 253 » Scatter-Add in Data Parallel Architectures |
ISCA
1999
IEEE
14 years 4 days ago
1999
IEEE
Value Prediction is a relatively new technique to increase instruction-level parallelism by breaking true data dependence chains. A value prediction architecture produces values, ...
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
IPPS
2000
IEEE
14 years 7 days ago
2000
IEEE
As processor speeds rapidly approach the Giga-Hertz regime, the disparity between process time and memory access time plays an increasing role in the overall limitation of processo...
VLDB
2007
ACM
14 years 8 months ago
2007
ACM
Low-latency and high-throughput processing are key requirements of data stream management systems (DSMSs). Hence, multi-core processors that provide high aggregate processing capa...
CAL
2008
13 years 8 months ago
2008
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...