This project is developing extended versions of RAIDs with low-power, and exploring novel energyefficient disk array architectures using coding techniques for data intensive compu...
This paper describes a reconfigurable architecture based on field-programmable gate-array (FPGA) technology for monitoring and analyzing network traffic at increasingly high networ...
Sherif Yusuf, Wayne Luk, Morris Sloman, Naranker D...
Since processor performance scalability will now mostly be achieved through thread-level parallelism, there is a strong incentive to parallelize a broad range of applications, inc...
Efficient data movement is an important part of any highperformance I/O system, but it is especially critical for the current and next-generation of massively parallel processing ...
Ron Oldfield, Patrick Widener, Arthur B. Maccabe, ...
The purpose of this paper is to demonstrate the implementation of an adaptable parallel architecture capable of system to task adaptation. The system implementation was based on X...