Sciweavers

1263 search results - page 44 / 253
» Scatter-Add in Data Parallel Architectures
Sort
View
ATS
2001
IEEE
126views Hardware» more  ATS 2001»
14 years 21 days ago
Design of an Optimal Test Access Architecture Using a Genetic Algorithm
Test access is a major problem for core-based systemon-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms...
Zahra Sadat Ebadi, André Ivanov
IJCIS
1998
116views more  IJCIS 1998»
13 years 8 months ago
Distributed Query Scheduling Service: An Architecture and Its Implementation
We present the systematic design and development of a distributed query scheduling service DQS in the context of DIOM, a distributed and interoperable query mediation system 26 ...
Ling Liu, Calton Pu, Kirill Richine
HPCA
2007
IEEE
14 years 9 months ago
Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications
Chip multiprocessors with multiple simpler cores are gaining popularity because they have the potential to drive future performance gains without exacerbating the problems of powe...
Hongtao Zhong, Steven A. Lieberman, Scott A. Mahlk...
INFOCOM
2008
IEEE
14 years 3 months ago
Beyond TCAMs: An SRAM-Based Parallel Multi-Pipeline Architecture for Terabit IP Lookup
—Continuous growth in network link rates poses a strong demand on high speed IP lookup engines. While Ternary Content Addressable Memory (TCAM) based solutions serve most of toda...
Weirong Jiang, Qingbo Wang, Viktor K. Prasanna
EUROPAR
2009
Springer
14 years 28 days ago
StarPU: A Unified Platform for Task Scheduling on Heterogeneous Multicore Architectures
Abstract. In the field of HPC, the current hardware trend is to design multiprocessor architectures that feature heterogeneous technologies such as specialized coprocessors (e.g., ...
Cédric Augonnet, Samuel Thibault, Raymond N...