174 search results - page 12 / 35 » Schedule-aware performance estimation of communication archi... |
HPCA
2003
IEEE
14 years 8 months ago
2003
IEEE
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
VLSI
2012
Springer
12 years 3 months ago
2012
Springer
e technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set sim...
SAMOS
2007
Springer
14 years 2 months ago
2007
Springer
As multi-processor system-on-chip (MPSoC) has become an effective solution to ever-increasing design complexity of modern embedded systems, fast and accurate HW/SW cosimulation of...
ISCA
2012
IEEE
11 years 10 months ago
2012
IEEE
Soft error reliability has become a first-order design criterion for modern microprocessors. Architectural Vulnerability Factor (AVF) modeling is often used to capture the probab...
CONCURRENCY
2000
13 years 7 months ago
2000
The Virtual Interface (VI) architecture has become the industry standard for user-level network interfaces. This paper presents the implementation and evaluation of Javia, a Java ...