174 search results - page 13 / 35 » Schedule-aware performance estimation of communication archi... |
ISCA
1998
IEEE
14 years 7 days ago
1998
IEEE
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a scalable and cost-effective mesh network at a constant cost per node. The MIT Al...
ISPASS
2006
IEEE
14 years 2 months ago
2006
IEEE
Detailed microarchitectural simulators are not well suited for exploring large design spaces due to their excessive simulation times. We introduce AXCIS, a framework for fast and ...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simul...
VLSID
2008
IEEE
14 years 8 months ago
2008
IEEE
Power consumption, physical size, and architecture design of sensor node processors have been the focus of sensor network research in the architecture community. What lies at the ...
EH
2004
IEEE
13 years 11 months ago
2004
IEEE
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...