Sciweavers

240 search results - page 6 / 48
» Scheduling Timed Modules for Correct Resource Sharing
Sort
View
DAC
1998
ACM
13 years 12 months ago
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
Ganesh Lakshminarayana, Niraj K. Jha
RTSS
2002
IEEE
14 years 15 days ago
Soft Real- Time Scheduling on Simultaneous Multithreaded Processors
Simultaneous multithreading (SMT) improves processor throughput by processing instructions from multiple threads each cycle. This is the first work to explore soft real-time sche...
Rohit Jain, Christopher J. Hughes, Sarita V. Adve
EMSOFT
2001
Springer
14 years 2 days ago
Rate-Based Resource Allocation Models for Embedded Systems
: Run-time executives and operating system kernels for embedded systems have long relied exclusively on static priority scheduling of tasks to ensure timing constraints and other c...
Kevin Jeffay, Steve Goddard
POLICY
2004
Springer
14 years 28 days ago
DecisionQoS: An Adaptive, Self-Evolving QoS Arbitration Module for Storage Systems
As a consequence of the current trend towards consolidating computing, storage and networking infrastructures into large centralized data centers, applications compete for shared ...
Sandeep Uttamchandani, Guillermo A. Alvarez, Gul A...
VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
14 years 8 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty