This paper describes a scheme to implement a shared address space of size m on an n-node mesh, with m polynomial in n, where each mesh node hosts a processor and a memory module. A...
Andrea Pietracaprina, Geppino Pucci, Jop F. Sibeyn
We consider a classic multidimensional generalization of the bin packing problem, namely, packing d-dimensional rectangles into the minimum number of unit cubes. Our two results a...
Abstract. This paper formalizes the security adversarial games for online symmetric cryptosystems in a unified framework for deterministic and probabilistic encryption schemes. On...
Pierre-Alain Fouque, Antoine Joux, Guillaume Poupa...
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...