133 search results - page 17 / 27 » Seamless integration of layout and simulation |
SBCCI
2006
ACM
14 years 1 months ago
2006
ACM
This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimizatio...
ICCAD
2000
IEEE
13 years 11 months ago
2000
IEEE
We present an error catch and analysis (ECA) system for semiconductor memories. The system consists of a test algorithm generator called TAGS, a fault simulator called RAMSES, and...
VLSID
2000
IEEE
13 years 11 months ago
2000
IEEE
The test signal method can be used to measure and model inductance parameters (self and mutual) of a very small interconnect especially in highdensity IC’s by using a test signa...
JCP
2008
13 years 7 months ago
2008
Semiconductor manufacturing process scaling increases leakage and transistor variations, both of which are problematic for static random access memory (SRAM). Since SRAM is a criti...
MICCAI
2009
Springer
14 years 8 months ago
2009
Springer
Recent advances in biophotonics have enabled in-vivo, in-situ histopathology for routine clinical applications. The non-invasive nature of these optical `biopsy' techniques, h...