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» Secure Configuration of Field Programmable Gate Arrays
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INTEGRATION
2008
127views more  INTEGRATION 2008»
13 years 6 months ago
A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver
This paper presents a Viterbi Decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has b...
Lucia Bissi, Pisana Placidi, Giuseppe Baruffa, And...
FPGA
2009
ACM
183views FPGA» more  FPGA 2009»
14 years 2 months ago
HW/SW methodologies for synchronization in FPGA multiprocessors
Modern Field Programmable Gate Arrays (FPGA) can be programmed with multiple soft-core processors. These solutions can be used for MultiProcessor Systems-on-Chip (MPSoCs) prototyp...
Antonino Tumeo, Christian Pilato, Gianluca Palermo...
IJCNN
2008
IEEE
14 years 1 months ago
Using Variable Neighborhood Search to improve the Support Vector Machine performance in embedded automotive applications
— In this work we show that a metaheuristic, the Variable Neighborhood Search (VNS), can be effectively used in order to improve the performance of the hardware–friendly versio...
Enrique Alba, Davide Anguita, Alessandro Ghio, San...
FPL
2007
Springer
115views Hardware» more  FPL 2007»
14 years 1 months ago
Hardware/Software Process Migration and RTL Simulation
This paper describes an execution cache that uses process migration between hardware and software contexts by way of run-time reconfiguration (RTR) of Field Programmable Gate Arr...
Aric D. Blumer, Cameron D. Patterson
IPPS
2006
IEEE
14 years 1 months ago
Parallel FPGA-based all-pairs shortest-paths in a directed graph
With rapid advances in VLSI technology, Field Programmable Gate Arrays (FPGAs) are receiving the attention of the Parallel and High Performance Computing community. In this paper,...
Uday Bondhugula, Ananth Devulapalli, Joseph Fernan...