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» Secure Configuration of Field Programmable Gate Arrays
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ISCAS
2003
IEEE
112views Hardware» more  ISCAS 2003»
14 years 24 days ago
Architectures for function evaluation on FPGAs
This paper presents a new family of architectures for multi-cycle area-efficient evaluation of elementary and composite functions, and an exploration of the design tradeoffs for i...
Nalin Sidahao, George A. Constantinides, Peter Y. ...
ARC
2009
Springer
134views Hardware» more  ARC 2009»
14 years 5 days ago
A HyperTransport 3 Physical Layer Interface for FPGAs
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...
Heiner Litz, Holger Fröning, Ulrich Brün...
FCCM
2009
IEEE
123views VLSI» more  FCCM 2009»
13 years 11 months ago
Scalable High Throughput and Power Efficient IP-Lookup on FPGA
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmab...
Hoang Le, Viktor K. Prasanna
FPL
2006
Springer
132views Hardware» more  FPL 2006»
13 years 11 months ago
Adaptive FPGAs: High-Level Architecture and a Synthesis Method
This paper presents preliminary work exploring adaptive field programmable gate arrays (AFPGAs). An AFPGA is adaptative in the sense that the functionality of subcircuits placed o...
Valavan Manohararajah, Stephen Dean Brown, Zvonko ...
IJNSEC
2007
137views more  IJNSEC 2007»
13 years 7 months ago
An FPGA-based AES-CCM Crypto Core For IEEE 802.11i Architecture
The widespread adoption of IEEE 802.11 wireless networks has brought its security paradigm under active research. One of the important research areas in this field is the realiza...
Arshad Aziz, Nassar Ikram