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» Secure Configuration of Field Programmable Gate Arrays
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DATE
2010
IEEE
134views Hardware» more  DATE 2010»
13 years 6 months ago
Combining optimizations in automated low power design
—Starting from sequential programs, we present an approach combining data reuse, multi-level MapReduce, and pipelining to automatically find the most power-efficient designs th...
Qiang Liu, Tim Todman, Wayne Luk
ISCAS
2008
IEEE
141views Hardware» more  ISCAS 2008»
14 years 1 months ago
ASPA: Focal Plane digital processor array with asynchronous processing capabilities
— In this paper we present implementation and experimental results for a digital vision chip that operates in mixed asynchronous/synchronous mode. Mixed configuration benefits fr...
Alexey Lopich, Piotr Dudek
ICPP
2008
IEEE
14 years 2 months ago
VELO: A Novel Communication Engine for Ultra-Low Latency Message Transfers
This paper presents a novel stateless, virtualized communication engine for sub-microsecond latency. Using a Field-Programmable-Gate-Array (FPGA) based prototype we show a latency...
Heiner Litz, Holger Fröning, Mondrian Nü...
CHES
2003
Springer
104views Cryptology» more  CHES 2003»
14 years 23 days ago
Power-Analysis Attacks on an FPGA - First Experimental Results
Field Programmable Gate Arrays (FPGAs) are becoming increasingly popular, especially for rapid prototyping. For implementations of cryptographic algorithms, not only the speed and ...
Siddika Berna Örs, Elisabeth Oswald, Bart Pre...
CHES
2004
Springer
106views Cryptology» more  CHES 2004»
13 years 11 months ago
XTR Implementation on Reconfigurable Hardware
Abstract. Recently, Lenstra and Verheul proposed an efficient cryptosystem called XTR. This system represents elements of F p6 with order dividing p2 -p+1 by their trace over Fp2 ....
Eric Peeters, Michael Neve, Mathieu Ciet