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ISCAS
2007
IEEE
161views Hardware» more  ISCAS 2007»
14 years 2 months ago
Hardware Architecture of a Parallel Pattern Matching Engine
Abstract— Several network security and QoS applications require detecting multiple string matches in the packet payload by comparing it against predefined pattern set. This proc...
Meeta Yadav, Ashwini Venkatachaliah, Paul D. Franz...
CODES
2010
IEEE
13 years 5 months ago
Hardware/software optimization of error detection implementation for real-time embedded systems
This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant realtime distributed embedded systems used for safe...
Adrian Lifa, Petru Eles, Zebo Peng, Viacheslav Izo...
ICEIS
2005
IEEE
14 years 2 months ago
Conditions for Interoperability
Abstract: Interoperability for information systems remains a challenge both at the semantic and organisational levels. The original three-level architecture for local databases nee...
B. Nick Rossiter, Michael A. Heather
HPDC
2010
IEEE
13 years 8 months ago
A GPU accelerated storage system
Massively multicore processors, like, for example, Graphics Processing Units (GPUs), provide, at a comparable price, a one order of magnitude higher peak performance than traditio...
Abdullah Gharaibeh, Samer Al-Kiswany, Sathish Gopa...
DRM
2006
Springer
14 years 6 days ago
The problem with rights expression languages
In this paper we consider the functionality that a rights expression language (REL) should provide within a digital rights management (DRM) environment. We begin by noting the dea...
Pramod A. Jamkhedkar, Gregory L. Heileman, Iv&aacu...