1210 search results - page 60 / 242 » Secure Logic Synthesis |
LOPSTR
2001
Springer
14 years 2 months ago
2001
Springer
In this paper we define a sequent calculus to formally specify, simulate, debug and verify security protocols. In our sequents we distinguish between the current knowledge of prin...
ISQED
2003
IEEE
14 years 3 months ago
2003
IEEE
In this paper, we propose a new physical synthesis methodology, PDL, which relaxes the timing constraints to obtain best optimality in terms of layout quality and timing quality. ...
DATE
1999
IEEE
1999
IEEE
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs
14 years 2 months ago
This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization ...
CD
2004
Springer
14 years 3 months ago
2004
Springer
Abstract. The secure deployment of components is widely recognized as a crucial problem in component-based software engineering. While major effort is concentrated on preventing ma...
SP
2000
IEEE
14 years 2 months ago
2000
IEEE
We describe the design and implementation of a security infrastructure for a distributed Java application. This work is inspired by SDSI/SPKI, but has a few twists of its own. We ...