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DATE
2009
IEEE
103views Hardware» more  DATE 2009»
14 years 4 months ago
Masking timing errors on speed-paths in logic circuits
There is a growing concern about timing errors resulting from design marginalities and the effects of circuit aging on speed-paths in logic circuits. This paper presents a low ove...
Mihir R. Choudhury, Kartik Mohanram
CCS
2005
ACM
14 years 3 months ago
Formal security analysis of basic network-attached storage
We study formal security properties of network-attached storage (NAS) in an applied pi calculus. We model NAS as an implementation of a specification based on traditional central...
Avik Chaudhuri, Martín Abadi
COMPSAC
2003
IEEE
14 years 3 months ago
A Security Characterisation Framework for Trustworthy Component Based Software Systems
This paper explores how to characterise security properties of software components, and how to reason about their suitability for a trustworthy compositional contract. Our framewo...
Khaled M. Khan, Jun Han
GLVLSI
2010
IEEE
209views VLSI» more  GLVLSI 2010»
14 years 3 months ago
Enhancing debugging of multiple missing control errors in reversible logic
Researchers are looking for alternatives to overcome the upcoming limits of conventional hardware technologies. Reversible logic thereby established itself as a promising directio...
Jean Christoph Jung, Stefan Frehse, Robert Wille, ...
DATE
2009
IEEE
140views Hardware» more  DATE 2009»
14 years 4 months ago
Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors
Carbon Nanotube Field-Effect Transistors (CNFETs) show big promise as extensions to silicon-CMOS because: 1) Ideal CNFETs can provide significant energy and performance benefits o...
Subhasish Mitra, Jie Zhang, Nishant Patil, Hai Wei