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ICCAD
2007
IEEE
103views Hardware» more  ICCAD 2007»
14 years 7 months ago
Enhancing design robustness with reliability-aware resynthesis and logic simulation
While circuit density and power efficiency increase with each major advance in IC technology, reliability with respect to soft errors tends to decrease. Current solutions to this...
Smita Krishnaswamy, Stephen Plaza, Igor L. Markov,...
DATE
2008
IEEE
121views Hardware» more  DATE 2008»
14 years 4 months ago
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthe...
Irith Pomeranz, Sudhakar M. Reddy
JELIA
2004
Springer
14 years 3 months ago
Towards a Logical Analysis of Biochemical Pathways
Biochemical pathways or networks are generic representations used to model many different types of complex functional and physical interactions in biological systems. Models based ...
Patrick Doherty, Steve Kertes, Martin Magnusson, A...
FPL
2000
Springer
128views Hardware» more  FPL 2000»
14 years 1 months ago
Verification of Dynamically Reconfigurable Logic
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
David Robinson, Patrick Lysaght
INTEGRATION
2006
82views more  INTEGRATION 2006»
13 years 10 months ago
On whitespace and stability in physical synthesis
In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible ...
Saurabh N. Adya, Igor L. Markov, Paul G. Villarrub...