As levels of parallelism are becoming increasingly complex in multiprocessor architectures, GALS, and asynchronous circuits, methodologies and software tools are needed to verify ...
Nicolas Coste, Hubert Garavel, Holger Hermanns, Ri...
Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite thei...
Konrad J. Kulikowski, Alexander B. Smirnov, Alexan...
Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. A low latency asynchronous wormhole route...
The power of side-channel leakage attacks on cryptographic implementations is evident. Today's practical defenses are typically attack-specific countermeasures against certain...
In recent years, some countermeasures against Differential Power Analysis (DPA) at the logic level have been proposed. At CHES 2005 conference, Popp and Mangard proposed a new coun...