9 search results - page 2 / 2 » Selecting partial scan flip-flops for circuit partitioning |
VLSID
1998
IEEE
13 years 12 months ago
1998
IEEE
A partial scan selection strategy is proposed in which flip-flops are selected via newly proposed dynamic reachability and observability measures such that the remaining hard-to-d...
TCAD
1998
13 years 7 months ago
1998
Conventional scan design imposes considerable area and delay overhead by using larger scan
ip-
ops and additional scan wires without utilizing the functionality of the combinatio...
ICCAD
1996
IEEE
13 years 12 months ago
1996
IEEE
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...
DFT
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...