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JPDC
2007
100views more  JPDC 2007»
13 years 7 months ago
Deadlock-free connection-based adaptive routing with dynamic virtual circuits
Virtual circuits can reduce routing overheads with irregular topologies and provide support for a mix of quality of service (QOS) requirements. Information about network loads and...
Yoshio Turner, Yuval Tamir
ISQED
2007
IEEE
135views Hardware» more  ISQED 2007»
14 years 1 months ago
MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we use...
Natasa Miskov-Zivanov, Diana Marculescu
ITC
1998
IEEE
114views Hardware» more  ITC 1998»
13 years 11 months ago
BETSY: synthesizing circuits for a specified BIST environment
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
Zhe Zhao, Bahram Pouya, Nur A. Touba
ATS
2009
IEEE
138views Hardware» more  ATS 2009»
14 years 2 months ago
Test Pattern Selection for Potentially Harmful Open Defects in Power Distribution Networks
Power distribution network (PDN) designs for today’s high performance integrated circuits (ICs) typically occupy a significant share of metal resources in the circuit, and henc...
Yubin Zhang, Lin Huang, Feng Yuan, Qiang Xu
CORR
2011
Springer
151views Education» more  CORR 2011»
13 years 2 months ago
A Simulation Experiment on a Built-In Self Test Equipped with Pseudorandom Test Pattern Generator and Multi-Input Shift Register
This paper investigates the impact of the changes of the characteristic polynomials and initial loadings, on behaviour of aliasing errors of parallel signature analyzer (Multi-Inp...
A. Ahmad